Digital multiplier circuits are typically implemented to multiply operands having very large bit sizes. In order to reduce the circuitry required to implement the multiplication operation, a recoding algorithm such as Modified Booth's algorithm is commonly utilized. A plurality of full adder circuits is commonly used to implement the addition of partial product bits to provide an output product. Some multipliers lose speed by having a structure which does not allow multiplication operations to be continuously generated. Such multipliers are structured so that there are periods of time during which no arithmetic operations are being implemented due to delays in providing intermediate operands necessary to continue the multiplication operation. Some multiplier structures are modified and commonly referred to as being "pipelined" in an effort to start a successive multiplication operation during any nonproductive time and before completion of an existing calculation. A typical problem associated with digital multipliers that are pipelined is that the full adders which are used to sum partial product bits cause delays due to propagation delays in the full adder circuits. Such delays in a multiplier are referred to as the "latency" of a multiplier. Even when a multiplier structure is pipelined, the latency of a multiplier may be significant for a multiplication of operands with many bits.